The invention relates to the communication of digital information, between multiple processors and a storage medium shared by these processors, using a packet bus. In particular, the invention provides the ability for the DSPs to store information to and retrieve information from a shared memory cache.
Digital signal processors can include memory space on the processor itself. DSP""s can also access memory external to the processor. When multiple DSP""s are configured together, such as on a common circuit board or on a single piece of silicon, or are grouped for use by a common application or set of applications, it is not uncommon for the DSP""s to access a common memory space. Access to a shared memory is typically accomplished through use of a separate processor for memory access control and a standard address bus and data bus arrangement.
Because of the ever increasing processing demands placed upon processors and the increasing restrictions on size, an increased need for memory space and memory access continues. For example, the DSPs of a VoIP system require access to a large amount of memory. Access can be provided directly through the host processor. Alternatively, due to the large number of DSPs that may reside in the signal processing farm, access to memory is preferably provided by a means that is independent of the host processor""s internal resources, so that the host processor is not overly taxed. Prior art solutions have approached the problem in two ways: (1) by providing each DSP with its own external memory unit; and/or (2) by providing a highly complex bus arbitration unit that can arbitrate and resolve the conflicting requests of multiple DSPs attempting to access the data and address busses of a large memory unit simultaneously.
Providing each DSP with its own independent memory unit is undesirable due to the high cost. Also independent memory does not allow easy pooling or sharing of common programs or information storage. Utilizing a bus arbitration unit, although less costly in terms of memory, can also be undesirable due to the cost and complexity.
The need for increased processing and memory access is illustrated, for example, in packet-based voice communication which has evolved to enable a single network to deliver integrated voice and data services. Network build-out based on packet technology can support converged networks carrying both voice and data. Large scale VoP networks have become increasingly feasible as DSP-based technology has been refined to provide lower power and higher densities. Silicon and software technology for VoP has evolved to support high channel density on a single chip.
The ability to scale VoP networks to large volumes of traffic is critical to service providers justifying deployment of a packet-based infrastructure. Scalability requires VoP gateways to support very high volumes of traffic without degradation of voice quality. This places increased pressure on gateway vendors to support thousands of voice channels on a single platform.
High density VoP architectures are driven by the following critical elements:
1) Power per channel of the solution;
2) Cost per channel of the solution;
3) Channel density of the solution;
4) System partitioning, including packet aggregation and routing;
5) Software features that define the functionality of the product; and
6) Network management capabilities.
Of primary importance to the present invention are the channel density, system partitioning, and software features of the product. FIG. 1 illustrates a high density VoP module having numerous DSPs 3 that convert voice signals, provided by packet bus 4, to the appropriate format as they migrate between a Public Switched Telephone Network (PSTN) and a packet network. All of the packet communications are conveyed by packet bus 4. The DSPs 3 are controlled by a xe2x80x9chostxe2x80x9d processor 5 that is responsible for configuring and downloading software to the DSPs 3, as well as assisting in call establishment, call termination, and other network management functions.
In order to concentrate a large number of VoP channels, aggregation logic 9 is required to:
1) Aggregate packet streams from multiple DSPs 3 to the backplane/packet network interface via packet bus 4;
2) Route incoming packets from the backplane/packet network interface to the appropriate DSP 3 via packet bus 4;
3) Provide a standard interface to the backplane/packet network interface; and
4) Filter network management and call setup/tear-down information to the host processor.
Software is a critical ingredient of high quality VoP systems. There are many features that must be implemented for carrier class systems. The most important software features are:
1) Echo cancellation;
2) Voice compression;
3) Packet play-out;
4) Tone processing;
5) Facsimile and modem support;
6) Packetization;
7) Signaling support; and
8) Network management.
Because a DSP is flexibly reconfigurable through software, the particular function a DSP is performing at some instant in time may be dynamically controlled by the host processor. When assigned a particular function by the host processor, such as voice processing or facsimile, the DSP downloads a program overlay for executing the function. When assigned a different function, the DSP dynamically downloads and executes the program overlay for this function. These program overlays use large amounts of memory for their long-term storage.
All communication between memory unit 6 and the DSPs 3 is conveyed by processor 5, used in conjunction with aggregation logic 9. In this manner, the DSP""s have only indirect communication with memory unit 6, conveyed through aggregation logic 9 and the host processor 5. When an indirect communication occurs, the host processor 5 must defer other pending operations to make the transfer.
High quality converged or integrated voice and data over packet V/DoP systems typically include a hardened line echo canceller that can properly cancel echo this can require significant memory space. Tone processing is essential for call setup and termination as well as handling in-call user functions, such as voice mail, credit card calls, etc. Standard voice announcements that need large amounts of memory are used in conjunction with the tone processing features. Also fundamental to any communication system is the need to discover, isolate, and remedy problems as quickly as possible, to minimize or eliminate the impact to users of the system. An ability to store diagnostic trace information for each DSP channel would greatly improve the performance and, thereby, the network management of the packet system. All of these features place high demands on the memory requirements of a packet system.
The present invention overcomes the memory access shortcomings of the prior art by providing a DSP memory cache connected to the packet bus. The DSP memory cache can be accessed directly by each of the DSP""s. Each DSP processor can request specific information from memory and can request information from specific memory locations. Requests for stored information are generated by a message unit that is internal to each DSP and are communicated over a packet bus to the shared memory device. The memory device can act upon the requests in the order in which they are received or can act according to a message priority. The requested information is sent to the requesting processor by a number of reply packets.
The DSPs communicate with the stored memory using the same packet format that is used to communicate with the network. This eliminates the need for a separate communication interface for the DSP and allows normal generation of packets which are written to memory and allows retrieval of voice playout to the network without additional CODEC processing.
A message-based memory system for Digital Signal Processor (DSP) storage expansion is disclosed, having: a packet communication bus; a number of DSPs each having a packet bus interface interconnected to the packet bus and a DSP message unit for generating packetized read and write requests to a memory device; and a memory device interconnected to the packet bus by a packet bus interface.